The invention relates generally to systems having more than one microprocessor and more particularly to methods for enabling intra-system communication between two processors.
Description of the Related Art
Many systems utilize more than one microprocessor in order to operate efficiently. Each of the processors may execute a different task, so that the tasks are performed simultaneously, rather than sequentially. Intra-system communications between processors allow cooperation in completing operations in substantially less time than would be required if a single processor were used. The architecture will vary depending upon the application.
Two types of architectures that are used in systems having more than one microprocessor may be referred to as a shared-memory multiprocessor architecture and a distributed-memory multiprocessor architecture. Inter-processor communications in the shared-memory architecture are achieved by means of shared, multi-port memory devices. A memory device is partitioned into separate modules, allowing the different processors to access the memory simultaneously. For inter-processor communications, a sending processor may store a message in memory and notify a destination processor of the memory address of the message. The destination processor may then fetch the message stored at that address. The message may be data or an instruction. A concern with this type of architecture is that the memory devices that allow the inter-processor communications may add significantly to the cost of the system. Another concern is that the architecture increases the hardware real estate requirements at the board level of the system.
Within the distributed-memory multiprocessor architecture, inter-processor communications are executed by passing messages. Each processor is equipped with its own local memory. The messages are sent from one processor to the local memory of the destination processor. The destination processor then accesses the message by accessing its own memory. The exchange of messages requires at least one data communication interface, such as a high-level data link control (HDLC) interface. This may significantly increase the cost, board real estate requirements, and power consumption of the system. U.S. Pat. No. 5,550,978 to Takahashi et al. describes a multiprocessor system having interfaces that allow communications between numerous processors. Each processor of the system has an interface for connecting in parallel to each of a number of asynchronous transfer mode (ATM) switches. Each interface splits a transmission data block into an array of bit data blocks. The interface converts the bit data blocks (e.g., messages) into cells by adding a header that includes the routing information to a destination processor. The interface then sends the cells in parallel to an array of ATM switches. The cells are transferred in parallel to the destination processor or processors by the ATM switches. The cells are then reassembled into the original data block at the interface of the destination processor.
The multiprocessor system of Takahashi et al. operates well for its intended purpose. However, the inter-processor communication technique requires a one-to-one correspondence between the processors and the interfaces. Moreover, an array of ATM switches is required. The number of ATM switches corresponds to the bit width of the internal buses of the processors. As previously noted, the required components add significantly to the cost, size and power consumption of the system.
What is needed is a system and method for enabling intra-system communication between two or more processors without adversely affecting other system-design concerns, such as providing a low power, low cost multiprocessor system.